Zoom V3 1612 Manual do Utilizador descarregar pdf (Página 45)

BIT1612 10-Bit Digital Video Decoder with OSD and T-CON

Vertical Scaling Filter Enable

0: Disable

R_SCY_FILTER_EN_M1 0x073[1] RW 1

1: Enable

Vertical Scaling Filter Enable on

Switch Mode 1

0: Bi-Linear Filter

R_SCY_FILTER_M1 0x073[2] RW 1

1: Box Filter

Vertical Pre-Scaling Down Enable

on Auto Switch Mode 1

0: Disable

R_LINE_CUT_M1 0x073[5] RW 1

1: Enable

Vertical Pre-Scaling Down Mode

on Auto Switch Mode 1

0: EVEN Line

R_CUT_MODE_M1 0x073[6] RW 1

1: ODD Line

Vertical Pre-Scaling Change Mode

on Auto Switch Mode 1

0: Manual (R_CUT_MODE)

R_CUT_AUTO_M1 0x073[7] RW 1

1: Auto (EVEN/ODD)

6.25 Timing Adjustment

BIT1612 Timing 調整原則：

1. IVREF (t1) 總長度與OVREF (t2) 相近且小於OVREF (t2) (參考 Figure 6-22)。

2. 修正 Line Buffer 所產生的 Error (Overflow or Underflow)。

Table 6-28 Timing Adjust Register

Mnemonic Address R/W Bits Description Default

R_MASTER_DLY_M0 0x074[7:0] RW 8

Output VSYNC Synchronize Delay

Time (Base on IHSYNC) on Switch

Mode 0

0x16

R_DLYE_OCLK_M0 0x077[3:0], 0x075[7:0] RW 12

Even Field Output VSYNC

Synchronize Delay Time (Base on

LCLK) on Switch Mode 0

0x075

R_DLYO_OCLK_M0 0x077[7:4], 0x076[7:0] RW 12

Odd Field Output VSYNC

Synchronize Delay Time (Base on

LCLK) on Switch Mode 0

0x071

R_MASTER_DLY_M1 0x078[7:0] RW 8

Output VSYNC Synchronize Delay

Time (Base on IHSYNC) on Switch

Mode 1

0x13

R_DLYE_OCLK_M1

0x07B[3:0],

0x079[7:0]

RW 12

Even Field Output VSYNC

Synchronize Delay Time(Base on

LCLK) on Switch Mode 1

0x266

R_DLYO_OCLK_M1

0x07B[7:4],

0x07A[7:0]

RW 12

Odd Field Output VSYNC

Synchronize Delay Time(Base on

LCLK) on Switch Mode 1

0x066

R_HCOUNT 0x169[6:0], 0x168[7:0] R 15 Horizontal Counter -

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 114 115

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